For example, an integrated circuit such as a large scale integration (LSI) may be designed by using individual macros that are circuit blocks each having different function made by dividing processing. Designed macros are placed in the integrated circuit, and the inter-macro wiring is designed. Subsequently, the overall performance of the integrated circuit is assessed.
Inside the integrated circuit, circuits are formed with multilayer wiring across a plurality of layers. Via holes are formed in the layers of the integrated circuit, and the macros are coupled to connecting wiring by leading terminals formed in the macros to one of the layers in which the connecting wiring is formed.
Related art is disclosed in Japanese Laid-open Patent Publication No. 6-139311, Japanese Laid-open Patent Publication No. 2006-268365, Japanese Laid-open Patent Publication No. 2000-353746, and International Publication Pamphlet No. WO 2009/084092.